(kicad_pcb (version 4) (host pcbnew 4.0.4-stable)
  (general
    (links 11)
    (no_connects 0)
    (area 125.425 60.405 182.825001 106.725)
    (thickness 1.6)
    (drawings 19)
    (tracks 34)
    (zones 0)
    (modules 10)
    (nets 8)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 1.5)
    (trace_clearance 3)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 1)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements 7FFFFFFF)
    (pcbplotparams
      (layerselection 0x010f0_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.100000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 0)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net 1 "Net-(F1-Pad1)")
  (net 2 "Net-(F1-Pad2)")
  (net 3 "Net-(P1-Pad2)")
  (net 4 "Net-(F2-Pad1)")
  (net 5 "Net-(F3-Pad2)")
  (net 6 "Net-(C2-Pad1)")
  (net 7 "Net-(C2-Pad2)")
  (net_class Default "This is the default net class."
    (clearance 3)
    (trace_width 1.5)
    (via_dia 1)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(C2-Pad1)")
    (add_net "Net-(C2-Pad2)")
    (add_net "Net-(F1-Pad1)")
    (add_net "Net-(F1-Pad2)")
    (add_net "Net-(F2-Pad1)")
    (add_net "Net-(P1-Pad2)")
  )
  (net_class DC ""
    (clearance 1)
    (trace_width 0.5)
    (via_dia 1)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
    (add_net "Net-(F3-Pad2)")
  )
  (module ASKicadLib:HLK-PM01 (layer F.Cu) (tedit 59F34A50)
    (at 161.77 84.27)
    (fp_text reference U1 (at -15.78 -9.33) (layer F.SilkS))
    (fp_text value HLK-PM01 (at -12.6 9.1) (layer F.Fab) hide)
    (pad 4 thru_hole circle (at 14.7 7.7) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 5 "Net-(F3-Pad2)"))
    (pad 3 thru_hole circle (at 14.7 -7.7) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 7 "Net-(C2-Pad2)"))
    (pad 2 thru_hole circle (at -14.7 2.5) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 4 "Net-(F2-Pad1)"))
    (pad 1 thru_hole circle (at -14.7 -2.5) (size 2 2) (drill 1) (layers *.Cu *.Mask)
      (net 3 "Net-(P1-Pad2)"))
  )
  (module Terminal_Blocks:TerminalBlock_Philmore_TB132_02x5mm_Straight (layer F.Cu) (tedit 59F3490B)
    (at 138.39 75.16 270)
    (descr "2-way 5.0mm pitch terminal block, http://www.philmore-datak.com/mc/Page%20197.pdf")
    (tags "screw terminal block")
    (fp_text reference P1 (at -1.7 -3.91 360) (layer F.SilkS))
    (fp_text value CONN_01X02 (at 2.6 9.19 270) (layer F.Fab) hide)
    (fp_text user %R (at 2.5 0.3 270) (layer F.Fab) hide)
    (pad 1 thru_hole rect (at 0 0 270) (size 2.4 2.4) (drill 1.47) (layers *.Cu *.Mask)
      (net 1 "Net-(F1-Pad1)"))
    (pad 2 thru_hole circle (at 5 0 270) (size 2.4 2.4) (drill 1.47) (layers *.Cu *.Mask)
      (net 3 "Net-(P1-Pad2)"))
    (model ${KISYS3DMOD}/Connectors_Terminal_Blocks.3dshapes/TerminalBlock_Philmore_TB132_02x5mm_Straight.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Terminal_Blocks:TerminalBlock_Philmore_TB132_02x5mm_Straight (layer F.Cu) (tedit 59F348EF)
    (at 136.43 95.95)
    (descr "2-way 5.0mm pitch terminal block, http://www.philmore-datak.com/mc/Page%20197.pdf")
    (tags "screw terminal block")
    (fp_text reference P2 (at -1.54 -3.92) (layer F.SilkS))
    (fp_text value CONN_01X02 (at 2.5 6.9) (layer F.Fab) hide)
    (fp_text user %R (at 2.5 0.3) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0) (size 2.4 2.4) (drill 1.47) (layers *.Cu *.Mask)
      (net 7 "Net-(C2-Pad2)"))
    (pad 2 thru_hole circle (at 5 0) (size 2.4 2.4) (drill 1.47) (layers *.Cu *.Mask)
      (net 6 "Net-(C2-Pad1)"))
    (model ${KISYS3DMOD}/Connectors_Terminal_Blocks.3dshapes/TerminalBlock_Philmore_TB132_02x5mm_Straight.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Varistors:RV_Disc_D12_W3.9_P7.5 (layer F.Cu) (tedit 59F38E70)
    (at 142.49 86.06 180)
    (tags "varistor SIOV")
    (fp_text reference Varistor (at 3.6 0.76 180) (layer F.SilkS))
    (fp_text value VR (at 3.75 -2.25 180) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at 0 0 180) (size 1.8 1.8) (drill 0.8) (layers *.Cu *.Mask)
      (net 4 "Net-(F2-Pad1)"))
    (pad 2 thru_hole circle (at 7.5 1.4 180) (size 1.8 1.8) (drill 0.8) (layers *.Cu *.Mask)
      (net 3 "Net-(P1-Pad2)"))
  )
  (module Resistors_ThroughHole:R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal (layer F.Cu) (tedit 59F348FE)
    (at 134.01 68.28)
    (descr "Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf")
    (tags "Resistor Axial_DIN0617 series Axial Horizontal pin pitch 20.32mm 2W length 17mm diameter 6mm")
    (fp_text reference F1 (at 2.6 2.31) (layer F.SilkS))
    (fp_text value FUSE (at 10.16 4.06) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at 0 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 1 "Net-(F1-Pad1)"))
    (pad 2 thru_hole oval (at 20.32 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 2 "Net-(F1-Pad2)"))
    (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.393701 0.393701 0.393701))
      (rotate (xyz 0 0 0))
    )
  )
  (module Resistors_ThroughHole:R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal (layer F.Cu) (tedit 59F34903)
    (at 178.35 68.24 180)
    (descr "Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf")
    (tags "Resistor Axial_DIN0617 series Axial Horizontal pin pitch 20.32mm 2W length 17mm diameter 6mm")
    (fp_text reference F2 (at 17.68 -2.24 180) (layer F.SilkS))
    (fp_text value FUSE (at 10.16 4.06 180) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at 0 0 180) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 4 "Net-(F2-Pad1)"))
    (pad 2 thru_hole oval (at 20.32 0 180) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 2 "Net-(F1-Pad2)"))
    (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.393701 0.393701 0.393701))
      (rotate (xyz 0 0 0))
    )
  )
  (module Resistors_ThroughHole:R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal (layer F.Cu) (tedit 59F34411)
    (at 157.43 97.99)
    (descr "Resistor, Axial_DIN0617 series, Axial, Horizontal, pin pitch=20.32mm, 2W, length*diameter=17*6mm^2, http://www.vishay.com/docs/20128/wkxwrx.pdf")
    (tags "Resistor Axial_DIN0617 series Axial Horizontal pin pitch 20.32mm 2W length 17mm diameter 6mm")
    (fp_text reference F3 (at 2.66 2.25) (layer F.SilkS))
    (fp_text value FUSE (at 10.16 4.06) (layer F.Fab) hide)
    (pad 1 thru_hole circle (at 0 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 6 "Net-(C2-Pad1)"))
    (pad 2 thru_hole oval (at 20.32 0) (size 2.4 2.4) (drill 1.2) (layers *.Cu *.Mask)
      (net 5 "Net-(F3-Pad2)"))
    (model ${KISYS3DMOD}/Resistors_THT.3dshapes/R_Axial_DIN0617_L17.0mm_D6.0mm_P20.32mm_Horizontal.wrl
      (at (xyz 0 0 0))
      (scale (xyz 0.393701 0.393701 0.393701))
      (rotate (xyz 0 0 0))
    )
  )
  (module graphicslogo:OpenSourceLogo_1000x1000_neg (layer F.Cu) (tedit 0)
    (at 161.38 82.53)
    (fp_text reference G*** (at 0 0) (layer F.SilkS) hide)
    (fp_text value LOGO (at 0.75 0) (layer F.SilkS) hide)
  )
  (module Capacitors_ThroughHole:CP_Radial_D5.0mm_P2.50mm (layer F.Cu) (tedit 59F39417)
    (at 153.13 96.91 270)
    (descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=5mm, Electrolytic Capacitor")
    (tags "CP Radial series Radial pin pitch 2.50mm  diameter 5mm Electrolytic Capacitor")
    (fp_text reference C1 (at 4.47 0.02 360) (layer F.SilkS))
    (fp_text value C (at 1.25 3.81 270) (layer F.Fab))
    (fp_text user %R (at 1.25 0 270) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
    (pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask))
    (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/CP_Radial_D5.0mm_P2.50mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (module Capacitors_ThroughHole:CP_Radial_D5.0mm_P2.50mm (layer F.Cu) (tedit 59F3941B)
    (at 147.28 96.91 270)
    (descr "CP, Radial series, Radial, pin pitch=2.50mm, , diameter=5mm, Electrolytic Capacitor")
    (tags "CP Radial series Radial pin pitch 2.50mm  diameter 5mm Electrolytic Capacitor")
    (fp_text reference C2 (at 4.47 0.08 360) (layer F.SilkS))
    (fp_text value C (at 1.25 3.81 270) (layer F.Fab))
    (fp_text user %R (at 1.25 0 270) (layer F.Fab))
    (pad 1 thru_hole rect (at 0 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 6 "Net-(C2-Pad1)"))
    (pad 2 thru_hole circle (at 2.5 0 270) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
      (net 7 "Net-(C2-Pad2)"))
    (model ${KISYS3DMOD}/Capacitors_THT.3dshapes/CP_Radial_D5.0mm_P2.50mm.wrl
      (at (xyz 0 0 0))
      (scale (xyz 1 1 1))
      (rotate (xyz 0 0 0))
    )
  )
  (gr_text "Revision 1" (at 167.03 82.46 270) (layer F.SilkS))
  (gr_text "www.openhardware.io \nLicensed under CERN OHL v.1.2" (at 161.72 92.76) (layer F.SilkS))
  (gr_text "by sundberg84" (at 161.46 88.41) (layer F.SilkS))
  (gr_text "Breakout board" (at 161.37 78.24) (layer F.SilkS))
  (gr_text HLK-PM01 (at 161.37 76.86) (layer F.SilkS))
  (gr_text "HLK-PM01\nInput: 100-240 volts AC\nOutput:+5±0.2 volts DC\n\n" (at 172.95 84.21 270) (layer F.SilkS))
  (gr_text Neutral (at 131.71 80.16 270) (layer F.SilkS))
  (gr_text "5V DC\nGND / VCC" (at 138.72 89.02) (layer F.SilkS))
  (gr_text "AC Input: HOT" (at 131.68 72.25 270) (layer F.SilkS))
  (gr_text "Input fuse \n200 mA" (at 144.28 68.16) (layer F.SilkS))
  (gr_text "Termal fuse\n73dgr C recommended" (at 168.3 68.09) (layer F.SilkS))
  (gr_text "Output fuse\n600 mA" (at 167.9 97.96) (layer F.SilkS))
  (gr_line (start 180.64 64.57) (end 180.64 101.99) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 130.74 64.57) (end 130.75 64.57) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 130.74 101.99) (end 130.74 64.57) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 180.65 101.99) (end 180.65 101.98) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 130.74 101.99) (end 180.65 101.99) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 130.73 64.58) (end 130.91 64.58) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 130.73 64.57) (end 180.64 64.57) (angle 90) (layer Edge.Cuts) (width 0.15))
)
